V. YAMUNA , P. MEENAKSHI VIDYA , S. SUDHA. Design of Power Efficient Double Edge Triggered DLL Clock Generator. International Journal of Emerging Trends in Science and Technology, [S. l.], v. 4, n. 06, p. 5257–5260, 2017. Disponível em: http://ijetst.in/index.php/ijetst/article/view/1135. Acesso em: 23 dec. 2024.