Abstract

Low power is a big concern for any electronic device in the modern world. The Delay Locked Loop (DLL)
clock generators play a vital role in clock generator circuits, due to the low jitter accumulation and stability
in the output. The proposed Double Edge Triggering (DET) for DLL clock generators reduces the power
consumption on the clock network. The DLL is designed using single phase clocking scheme which
minimizes the delay deviation and phase errors. The clock generator is designed to operate at a frequency
of 500MHZ. The analysis is made between single edge triggered DLL and double edge triggered DLL and
the power consumed is found to be 5.328mW and 3.43mW respectively using 65nm CMOS process.